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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 7 Jun 2016
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      PicoRV32 now has >0.5 DMIPS/MHz (essentially by using newlib libc from @risc_v tools for building Dhrystone ;)https://github.com/cliffordwolf/picorv32 …

      1 reply 2 retweets 3 likes
    2. William D. Jones‏ @cr1901 7 Jun 2016
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      Replying to @oe1cxw

      CPI > 1... so this is a non-pipelined core, correct?

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 7 Jun 2016
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      Replying to @cr1901

      yes. (Except next insn is prefetched in background.)

      8:29 AM - 7 Jun 2016
      1 reply 0 retweets 0 likes
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        1. William D. Jones‏ @cr1901 7 Jun 2016
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          Replying to @oe1cxw

          750 6-input LUTs... I guess IceStick can't run it :(

          1 reply 0 retweets 0 likes
        2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 7 Jun 2016
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          Replying to @cr1901

          ice40 1k is not large enough. But it only needs about one quarter of the resources in an ice40 8k chip.

          1 reply 0 retweets 1 like
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