@oe1cxw Does Yosys have an option to not insert IOBs? Equivalent to "out_of_context" mode in Vivado?
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hmm.. Maybe this is a Vivado-side flag I need to select.. I thought the EDIF could propagate out_of_context metadata.. Let me check
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Ah thanks.. that works! :P
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Remarkably Verilog>yosys>EDIF>Vivado PR flow is ~10x faster than Verilog>Vivado synth>Vivado PR for direct instancing Xilinx prims.
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