Anyone up for extending the verilog output in objcopy to support 32/64-bit vectors? Currently everyone is doing their own version @antgreen
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@OlofKindgren@oe1cxw@antgreen probably best to define new targets verilog16, verilog32, verilog64
@jameyhicks @OlofKindgren @antgreen that would be fine with me. Whatever is easiest to implement.
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@oe1cxw@OlofKindgren@antgreen added --verilog-data-width option to objcopy https://github.com/cambridgehackers/binutils-gdb … -
@oe1cxw@OlofKindgren@antgreen it's a branch off the upstream master - Show replies
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@oe1cxw@OlofKindgren@antgreen unfortunately, that commit does not apply cleanly to riscv-binutils-gdb due to other commits -
@jameyhicks@oe1cxw@antgreen I need it for OpenRISC and that's in upstream binutils, so it should be ok
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@oe1cxw@OlofKindgren@antgreen and I need to add some test casesThanks. Twitter will use this to make your timeline better. UndoUndo
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