Slides for my #eh16 talk on Verilog Synthesis and Formal Verification with Yosys: http://www.clifford.at/papers/2016/yosys-synth-formal/ …
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Slides for my #eh16 talk on Verilog Synthesis and Formal Verification with Yosys: http://www.clifford.at/papers/2016/yosys-synth-formal/ …
