Prediction: TCL, LISP, and and Verilog will continue dominance as chip design languages for the next 25 years.
@adapteva I think Verilog will become a kind of standard IR between higher level HDLs (Chisel, C/OpenCL HLS, etc) and synthesis flows. 1/2
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@oe1cxw Agreed. High level synthesis has been around for 15 years. It was always C-HLS-->Verilog/VHDL-->ASIC tools-->GDS -
@adapteva@oe1cxw I strongly believe in elastic circuit design tools here are some references: https://github.com/drom/elastic
End of conversation
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