Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

#FPGA 1/ Yesterday at the 3rd @RISC_V Workshop I introduced GRVI Phalanx, an FPGA Accelerator Accelerator.

#FPGA 2/ I described and demonstrated a 400-processor @RISC_V multiprocessor implemented in a @XilinxInc KU040 in a KCU105,

#FPGA 3/ organized into shared memory clusters and interconnected on a Hoplite NOC with 700 Gb/s bisection bandwidth.

#FPGA 4/ (I also demonstrated a 32 core system implemented in a @XilinxInc Artix-7 35T in a @DigilentInc Arty.)

#FPGA 5/ GRVI is an FPGA-efficient @RISC_V RV32I soft processor, designed to be a processing element in a multiprocessor.

#FPGA 6/ GRVI typically consumes 320 6-LUTs and currently runs at 300-375 MHz in @XilinxInc Kintex UltraScale (-2).

#FPGA 7/ Phalanx is parallel FPGA accelerator framework, designed to reduce the effort and cost of building FPGA accelerators.

#FPGA 8/ A Phalanx is a composition of clusters of soft CPUS & accelerators, w/ high bandwidth memory & I/O interfaces on a Hoplite NOC.