Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw Of course there has to be ways to store the FPGA bitstream to configure the LUTs used to implement logic. What's throwing me off >>

@oe1cxw is how its possible to represent a bitstream in pure Verilog when it depends on things inside the FPGA not exposed to the programmer

@cr1901 like what?

@oe1cxw Whatever logic element (prob a latch) is used inside the FPGA to talk to the LUTs and say: "These are your values you should store".

@oe1cxw I don't actually know how an FPGA loads it's bitstream, but I assume the parts that load it into the LUTs are programmer-inassecible

@oe1cxw Will IceStorm docs alleviate my confusion? Or is knowing HOW an FPGA loads its bitstream a prereq to understanding?

@cr1901 I think there is confusion about what the code the OP posted is: It's just a "decompiled" bit-stream. Nothing read back from the IC.

@oe1cxw I guess my question is: What is a decompiled bitstream then? Modifying something FROM VERILOG that's ultimately stored in a Flash >>