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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. William D. Jones‏ @cr1901 18 Dec 2015
      • Report Tweet
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      Replying to @cr1901

      @oe1cxw which are used to determine the contents of these LUTs? Does Lattice provide primitives to access the LUT configuration?

      1 reply 0 retweets 0 likes
    2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 Dec 2015
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      Replying to @cr1901

      @cr1901 You know what Project Icestorm is? There are no Lattice tools used..

      1 reply 0 retweets 0 likes
    3. William D. Jones‏ @cr1901 18 Dec 2015
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      Replying to @oe1cxw

      @oe1cxw It's an OSS toolchain to program Lattice FPGAs, right?

      3 replies 0 retweets 0 likes
    4. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 Dec 2015
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      Replying to @cr1901

      @cr1901 But of course there are also other tools to inspect bitstreams and also "decompile" them back to verilog.

      1 reply 0 retweets 0 likes
    5. William D. Jones‏ @cr1901 18 Dec 2015
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      Replying to @oe1cxw

      @oe1cxw Of course there has to be ways to store the FPGA bitstream to configure the LUTs used to implement logic. What's throwing me off >>

      1 reply 0 retweets 0 likes
    6. William D. Jones‏ @cr1901 18 Dec 2015
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      Replying to @cr1901

      @oe1cxw is how its possible to represent a bitstream in pure Verilog when it depends on things inside the FPGA not exposed to the programmer

      1 reply 0 retweets 0 likes
    7. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 Dec 2015
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      Replying to @cr1901

      @cr1901 like what?

      1 reply 0 retweets 0 likes
    8. William D. Jones‏ @cr1901 18 Dec 2015
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      Replying to @oe1cxw

      @oe1cxw Whatever logic element (prob a latch) is used inside the FPGA to talk to the LUTs and say: "These are your values you should store".

      1 reply 0 retweets 0 likes
    9. William D. Jones‏ @cr1901 18 Dec 2015
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      Replying to @cr1901

      @oe1cxw I don't actually know how an FPGA loads it's bitstream, but I assume the parts that load it into the LUTs are programmer-inassecible

      1 reply 0 retweets 0 likes
    10. William D. Jones‏ @cr1901 18 Dec 2015
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      Replying to @cr1901

      @oe1cxw Will IceStorm docs alleviate my confusion? Or is knowing HOW an FPGA loads its bitstream a prereq to understanding?

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 Dec 2015
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      Replying to @cr1901

      @cr1901 I think there is confusion about what the code the OP posted is: It's just a "decompiled" bit-stream. Nothing read back from the IC.

      2:28 PM - 18 Dec 2015
      1 reply 0 retweets 0 likes
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        1. William D. Jones‏ @cr1901 18 Dec 2015
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          Replying to @oe1cxw

          @oe1cxw I guess my question is: What is a decompiled bitstream then? Modifying something FROM VERILOG that's ultimately stored in a Flash >>

          3 replies 0 retweets 0 likes
        2. William D. Jones‏ @cr1901 18 Dec 2015
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          Replying to @cr1901

          @oe1cxw ROM doesn't seem all that useful.

          1 reply 0 retweets 0 likes
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