@alexcweiner @cr1901 @scanlime Its better for re-synthesis than writing something like "16'b 1100111100001100 >> {in1, in2, in3, in4}".
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@oe1cxw It's an OSS toolchain to program Lattice FPGAs, right?
@cr1901 But of course there are also other tools to inspect bitstreams and also "decompile" them back to verilog.
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@oe1cxw Of course there has to be ways to store the FPGA bitstream to configure the LUTs used to implement logic. What's throwing me off >> -
@oe1cxw is how its possible to represent a bitstream in pure Verilog when it depends on things inside the FPGA not exposed to the programmer - Show replies
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