Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@alexcweiner @cr1901 @scanlime Its better for re-synthesis than writing something like "16'b 1100111100001100 >> {in1, in2, in3, in4}".

@oe1cxw @alexcweiner @scanlime I didn't know you could even access the configuration using Verilog code o.0;

@oe1cxw I thought Verilog code maps to the contents of LUTs inside the FPGA. How does Verilog give you access to the parts of the FPGA >>

@oe1cxw which are used to determine the contents of these LUTs? Does Lattice provide primitives to access the LUT configuration?