@alexcweiner @cr1901 @scanlime Its better for re-synthesis than writing something like "16'b 1100111100001100 >> {in1, in2, in3, in4}".
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@oe1cxw I thought Verilog code maps to the contents of LUTs inside the FPGA. How does Verilog give you access to the parts of the FPGA >>
@cr1901 You can of course instantiate FPGA primitives, but this is an FPGA bit-stream converted back to behavioral Verilog.
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