@oe1cxw @alexcweiner @scanlime I didn't know you could even access the configuration using Verilog code o.0;
@alexcweiner @cr1901 @scanlime Its better for re-synthesis than writing something like "16'b 1100111100001100 >> {in1, in2, in3, in4}".
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@cr1901@alexcweiner@scanlime It's actually one of the first things I published for Project Icestorm:https://www.youtube.com/watch?v=u1ZHcSNDQMM … - Show replies
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