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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 4 Dec 2015
    • Report Tweet
    • Report NetzDG Violation

    The hardest part of building a complex reference design or demo for a brand new toolchain is knowing where to look for the bug..

    7:55 AM - 4 Dec 2015
    • 1 Retweet
    • 2 Likes
    • whitequark
    1 reply 1 retweet 2 likes
      1. New conversation
      1. William D. Jones‏ @cr1901 4 Dec 2015
        • Report Tweet
        • Report NetzDG Violation
        Replying to @oe1cxw

        @oe1cxw I wish yosys wasn't written in C++, then I could help T_T.

        1 reply 0 retweets 0 likes
      2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 4 Dec 2015
        • Report Tweet
        • Report NetzDG Violation
        Replying to @cr1901

        @cr1901 The bug wasn't in Yosys (or our P&R flow) anyways.. It also wasn't in the HDL design for the SoC design or its firmware..

        1 reply 0 retweets 0 likes
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