Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw @azonenberg Yes, I meant gates. Still nicely within "aww, it's so cute" territory.

@cr1901 @azonenberg PicoRV32 in smallest config, mapped with Yosys to a standard CMOS cell library: 4522 gates and 953 flip-flops.

@oe1cxw @azonenberg I wonder how a 6502 core would do (I like those as a compromise between Picoblaze and a full-blown RISC CPU)?

@cr1901 @azonenberg I know because I played around with the 6502 netlist a few years ago. E.g. http://svn.clifford.at/handicraft/2011/6502tsim/ …

@oe1cxw @azonenberg Yes, Visual6502 is amazing. Kinda shocking that it's STILL not enough to create a properly operating FPGA core. >>

@oe1cxw @azonenberg Apparently, analog effects that need to be emulated on the FPGA are enough to crash "DIP plug in" 6502 replacements.

@cr1901 @azonenberg "analog effects" is essentially the memory effect of floating lines.. Convertion from NMOS to Logic + SR-FFs works ok.

@cr1901 @azonenberg I planned on using this to create a logic+FF representation. But then other things became more interesting..