Idea: Add lots of tiny CPUs, say Cortex-M0, to FPGA fabric as hard IP. Quick estimate says 2x M0 are ~= size of one RAMB18 on same process
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Replying to @azonenberg
@azonenberg According to ARM website, Cortex M0 is about 12,000 transistors (which puts it nicely into "it's so damn cute" territory)?1 reply 0 retweets 0 likes -
Replying to @cr1901
@cr1901@azonenberg I seriously doubt the 12k _transistors_ figure. Are you sure you don't mean 12k _gates_?1 reply 0 retweets 0 likes -
Replying to @oe1cxw
@oe1cxw@azonenberg Yes, I meant gates. Still nicely within "aww, it's so cute" territory.2 replies 0 retweets 0 likes -
Replying to @cr1901
@cr1901@azonenberg PicoRV32 in smallest config, mapped with Yosys to a standard CMOS cell library: 4522 gates and 953 flip-flops.1 reply 0 retweets 0 likes -
Replying to @oe1cxw
@oe1cxw@azonenberg I wonder how a 6502 core would do (I like those as a compromise between Picoblaze and a full-blown RISC CPU)?2 replies 0 retweets 0 likes -
Replying to @cr1901
@cr1901@azonenberg The 6502 had 3510 NMOS transistors and 1018 pullup resistors.1 reply 0 retweets 0 likes -
Replying to @oe1cxw
@cr1901@azonenberg Or in other words: the 6502 had fewer transistors than the PicoRV32 has gates.1 reply 0 retweets 0 likes -
Replying to @oe1cxw
@cr1901@azonenberg But then, most of the PicoRV32 gates are related to the register file and the 6502 had no register file.1 reply 0 retweets 0 likes
@cr1901 @azonenberg 6502 used the zero page as quasi register file. So you'd had to add the transistors for the zero page in mem as well..
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