Idea: Add lots of tiny CPUs, say Cortex-M0, to FPGA fabric as hard IP. Quick estimate says 2x M0 are ~= size of one RAMB18 on same process
@cr1901 @azonenberg I seriously doubt the 12k _transistors_ figure. Are you sure you don't mean 12k _gates_?
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@oe1cxw@azonenberg Yes, I meant gates. Still nicely within "aww, it's so cute" territory. -
@cr1901@azonenberg PicoRV32 in smallest config, mapped with Yosys to a standard CMOS cell library: 4522 gates and 953 flip-flops. - Show replies
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