Just spent two days trying to find a bug in my Verilog code and/or Yosys. Bug was in Raspberry Pi firmware... #icoboard #ineedalogicanalyzer
Replying to @kristianpaul0
@kristianpaul0 No. Its a bit-parallel half-duplex interface. In one instance I forgot to switch to send mode before writing data to the fpga
1:24 AM - 8 Nov 2015
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