Just spent two days trying to find a bug in my Verilog code and/or Yosys. Bug was in Raspberry Pi firmware... #icoboard #ineedalogicanalyzer
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@cr1901 I plan to implement something similar, but with support from the synthesis tool for injecting the core (like eg Xilinx's Chipscope).
@cr1901 But the core I had problems with was the Raspi<->FPGA interface itself. I'm going to need that working for the debug core..
