Just spent two days trying to find a bug in my Verilog code and/or Yosys. Bug was in Raspberry Pi firmware... #icoboard #ineedalogicanalyzer
-
@oe1cxw I use@enjoy_digital's Litescope. Software is written in Python and can output to .VCD or Python arrays
@cr1901 I plan to implement something similar, but with support from the synthesis tool for injecting the core (like eg Xilinx's Chipscope).
-
-
@cr1901 But the core I had problems with was the Raspi<->FPGA interface itself. I'm going to need that working for the debug core..Thanks. Twitter will use this to make your timeline better. UndoUndo
-
-
-
@oe1cxw Not sure why injecting a logic analyzer core is necessary after the fact?Thanks. Twitter will use this to make your timeline better. UndoUndo
-
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.