Just spent two days trying to find a bug in my Verilog code and/or Yosys. Bug was in Raspberry Pi firmware... #icoboard #ineedalogicanalyzer
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@oe1cxw Use an FPGA one and buy some probes :P?
@cr1901 I do have an Open Workbench Logic Sniffer. But I never use it because it always takes a while to setup the Java software for it..
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@oe1cxw I use@enjoy_digital's Litescope. Software is written in Python and can output to .VCD or Python arrays -
@oe1cxw (I'm not sure if you're a Migen fan or not lol) - Show replies
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