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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 28 Oct 2015
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      Today I wrote my first little demo in @MyHDL. So far I like it more than @chiselhdl.. Thoughts / arguments / flame wars anyone?

      7 replies 3 retweets 9 likes
    2. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 28 Oct 2015
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      Replying to @oe1cxw

      @oe1cxw @MyHDL @chiselhdl Chisel is a terrible language, has no reason to exist. I'm surprised why anybody would waste any time on it.

      2 replies 0 retweets 1 like
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 28 Oct 2015
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      Replying to @nachiketkapre

      @nachiketkapre @MyHDL @chiselhdl that's a bit harsh! ;) so what is your opinion of MyHDL then?

      1 reply 0 retweets 0 likes
    4. Prof. Nachiket Kapre (he/him/il/lui)‏ @nachiketkapre 28 Oct 2015
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      Replying to @oe1cxw

      @oe1cxw @MyHDL @chiselhdl I haven't used MyHDL yet, but @Gord1ei raves about it.. Recently @jangray taught me to respect Verilog again :P

      1 reply 0 retweets 1 like
    5. Jan Gray‏ @jangray 28 Oct 2015
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      Replying to @nachiketkapre

      @nachiketkapre @oe1cxw @MyHDL @chiselhdl @Gord1ei Hand tech mapped, floor planned, structurally instantiated System Verilog?

      3 replies 0 retweets 3 likes
    6. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 28 Oct 2015
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      Replying to @jangray

      @jangray It sure gives you the control, but does it give you the productivity? Complex generators are hard to write in (System)Verilog..

      2 replies 1 retweet 2 likes
    7. Jan Gray‏ @jangray 29 Oct 2015
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      Replying to @oe1cxw

      @oe1cxw I used to build generators in C++ netlist generator class lib http://fpgacpu.org/cnets/log.html  etc. now write Python to write vlog / sys vlog

      2 replies 0 retweets 3 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 29 Oct 2015
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      Replying to @jangray

      @jangray I'm using custom Python to Verilog code generators now. I'm looking into MyHDL because I want to improve on that methodology..

      3:40 AM - 29 Oct 2015
      1 reply 0 retweets 0 likes
        1. Olof Kindgren‏ @OlofKindgren 29 Oct 2015
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          Replying to @oe1cxw

          @oe1cxw @jangray This is the same reason I started looking into Migen. To use it as a sort of standardized template writer

          0 replies 0 retweets 0 likes
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