Today I wrote my first little demo in @MyHDL. So far I like it more than @chiselhdl.. Thoughts / arguments / flame wars anyone?
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@nachiketkapre@oe1cxw@MyHDL @chiselhdl@Gord1ei Hand tech mapped, floor planned, structurally instantiated System Verilog?
@jangray It sure gives you the control, but does it give you the productivity? Complex generators are hard to write in (System)Verilog..
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@oe1cxw you're quite right, low productivity, unless you are measuring "time to achieve an optimal design" or the like -
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@oe1cxw I used to build generators in C++ netlist generator class lib http://fpgacpu.org/cnets/log.html etc. now write Python to write vlog / sys vlog -
@jangray@oe1cxw#ThrowbackThursday there were quite a few of those in that timeframe... - Show replies
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