Today I wrote my first little demo in @MyHDL. So far I like it more than @chiselhdl.. Thoughts / arguments / flame wars anyone?
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@oe1cxw However, the need for hierarchy and floorplanning for synthesis and layout is largely overrated. 2/2
@jandecaluwe_en It's not just floorplanning of course. There are many reasons for not wanting to synthesize a large design in one big piece.
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@oe1cxw What is "large"? A 100,000 gates / 5000 FFs design is a small cell by today's ASIC synthesis standards.Thanks. Twitter will use this to make your timeline better. UndoUndo
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