@oe1cxw proving hardcaml version of simlib.v cells for json import. all those annoying implicit verilog resizing rules. ~1276 proved so far
@evilkid btw: What are you trying to verify with yosys/sat. Anything related to Hardcaml?
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@evilkid Cool! Looking forward to see this in action. And yes, the signed/resize rules of verilog are tricky to get right.. ;)
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