Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@cr1901 oh no it's definitely better than literally writing out gates... which wouldn't match how FPGAs work either, anyway

@mnxmnkmnd Ahhh, I see now. Haven't really given that part much thought tbh. I wouldn't trust myself to correctly allocate LUTs.

@mnxmnkmnd Some subcircuits may need less than 4 inputs. Do I waste the other LUT inputs, or do I try to combine subcircuits into one?

@mnxmnkmnd @oe1cxw probably has more to say about this topic, since he wrote a synthesis system (sorry for volunteering you in advance1) :P.

@cr1901 @mnxmnkmnd There is a lot of talk about using different languages than verilog for design entry, but not because verilog maps [..]

@cr1901 @mnxmnkmnd [..] badly to hardware but because its is not user-friendly as design entry language. all attempts so far (Chisel, [..]

@cr1901 @mnxmnkmnd [..] MyHDL, etc.) generate Verilog (or VHDL), and no complaints so far about this. Re memories: different [..]

@cr1901 @mnxmnkmnd [..] architectures support different things in memories (sync or async read, different number of ports, mixing of [..]