@mnxmnkmnd In my experience, it's easier to read the intent behind behavioral Verilog and map it to gates, than to just see and/or all over
-
@cr1901@mnxmnkmnd [..] clock domains, etc.) when you are done abstracting all that away you pretty much end up with verilog arrays, so [..]
@cr1901 @mnxmnkmnd [..] its not that verilog arrays are bad at modelling RAM, its that some RAM you can model is not compatible with [..]
-
-
@cr1901@mnxmnkmnd [..] the type of FPGA you are using. -
@oe1cxw@mnxmnkmnd Wow, you went above and beyond the call of duty with that answer :). I can't even find the RAM discussion anymore XD. - Show replies
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.