@cr1901 yeah, but it's written as this sequential abstraction that has nothing to do with circuits.
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@cr1901@mnxmnkmnd [..] architectures support different things in memories (sync or async read, different number of ports, mixing of [..]
@cr1901 @mnxmnkmnd [..] clock domains, etc.) when you are done abstracting all that away you pretty much end up with verilog arrays, so [..]
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@cr1901@mnxmnkmnd [..] its not that verilog arrays are bad at modelling RAM, its that some RAM you can model is not compatible with [..] -
@cr1901@mnxmnkmnd [..] the type of FPGA you are using. - Show replies
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