@mnxmnkmnd Verilog guarantees foo will take on the value 9 is conditions for idle are met, 0 otherwise.
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@cr1901@mnxmnkmnd [..] MyHDL, etc.) generate Verilog (or VHDL), and no complaints so far about this. Re memories: different [..]
@cr1901 @mnxmnkmnd [..] architectures support different things in memories (sync or async read, different number of ports, mixing of [..]
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@cr1901@mnxmnkmnd [..] clock domains, etc.) when you are done abstracting all that away you pretty much end up with verilog arrays, so [..] -
@cr1901@mnxmnkmnd [..] its not that verilog arrays are bad at modelling RAM, its that some RAM you can model is not compatible with [..] - Show replies
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