@cr1901 not if they're sequential, like, always @(...) foo = 0; case (state) idle: foo = 9; and so on.
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@cr1901@mnxmnkmnd [..] badly to hardware but because its is not user-friendly as design entry language. all attempts so far (Chisel, [..]
@cr1901 @mnxmnkmnd [..] MyHDL, etc.) generate Verilog (or VHDL), and no complaints so far about this. Re memories: different [..]
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@cr1901@mnxmnkmnd [..] architectures support different things in memories (sync or async read, different number of ports, mixing of [..] -
@cr1901@mnxmnkmnd [..] clock domains, etc.) when you are done abstracting all that away you pretty much end up with verilog arrays, so [..] - Show replies
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@oe1cxw@cr1901@mnxmnkmnd Verilog works well for an IR and a pragmatic for an implementation path.Thanks. Twitter will use this to make your timeline better. UndoUndo
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