@mnxmnkmnd I don't think that; Verilog compilers tend to pattern match specific constructs to internal primitives, such as MUX, FSM, etc.
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@mnxmnkmnd@oe1cxw probably has more to say about this topic, since he wrote a synthesis system (sorry for volunteering you in advance1) :P.
@cr1901 @mnxmnkmnd There is a lot of talk about using different languages than verilog for design entry, but not because verilog maps [..]
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@cr1901@mnxmnkmnd [..] badly to hardware but because its is not user-friendly as design entry language. all attempts so far (Chisel, [..] -
@cr1901@mnxmnkmnd [..] MyHDL, etc.) generate Verilog (or VHDL), and no complaints so far about this. Re memories: different [..] - Show replies
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