Just taped out my first PCB with my Verilog-to-KiCAD flow! Super simple DIP-8 MCU dev board on one layer, but gotta start somewhere @oe1cxw
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Replying to @azonenberg
@azonenberg@oe1cxw awesome! Did you document the build anywhere?1 reply 0 retweets 1 like -
Replying to @Chris_Gammell
@Chris_Gammell@oe1cxw See the comment thread for the RTL. The Yosys script is in the same directory, netlist converter is in src/rtl2pcb/2 replies 1 retweet 1 like -
Replying to @azonenberg
@azonenberg oh, nice! You wrote another RTLIL parser!2 replies 0 retweets 0 likes -
Replying to @oe1cxw
@azonenberg Out of curiosity: Did you consider the write_json format as exchange file format?1 reply 0 retweets 0 likes
Replying to @azonenberg
@azonenberg that s possible. It's less than 6 months old. Some info: http://scratch.clifford.at/yosys_json_help.txt … http://scratch.clifford.at/example.json
12:04 PM - 13 Oct 2015
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