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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 26 Aug 2015
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      @azonenberg Maybe you can answer the hardware/bitstream aspects of this question re Yosys and Xilinx XC9572XL? http://stackoverflow.com/questions/32217939/what-is-required-to-target-a-new-device …

      1 reply 0 retweets 0 likes
    2. Andrew Zonenberg‏ @azonenberg 26 Aug 2015
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      Replying to @oe1cxw

      @oe1cxw Didn't know you had SoP synthesis working with ABC. I might try integrating it with libcrowbar fairly soon.

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    3. Andrew Zonenberg‏ @azonenberg 26 Aug 2015
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      @oe1cxw The work I presented in my REcon talk is sufficient to synthesize combinatorial-only SoP netlists to bitstream already.

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    4. Andrew Zonenberg‏ @azonenberg 26 Aug 2015
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      Replying to @azonenberg

      @oe1cxw It won't be optimal techmapping (some advanced features won't be supported so packing density will suffer) but it will work.

      1 reply 0 retweets 0 likes
    5. Andrew Zonenberg‏ @azonenberg 26 Aug 2015
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      Replying to @azonenberg

      @oe1cxw Can you point me to some documentation on the ABC .pla file format?

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      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 26 Aug 2015
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      Replying to @azonenberg

      @azonenberg It's the good old espresso PLA format: http://www.ecs.umass.edu/ece/labs/vlsicad/ece667/links/espresso.5.html …

      10:10 PM - 26 Aug 2015
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