Finally released my FPGA video pipeline for VGA / DVI / HDMI / OpenLDI / LVDS (open source under ISC license):https://github.com/cliffordwolf/SimpleVOut …
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@oe1cxw nice! Are you using Yosis for synthesis?
@enjoy_digital Yosys 0.6 will have support for initialized xilinx block rams. I will make a demo with an embedded cpu and video then.
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@oe1cxw thanks, since Yosys is already integrated in Migen I will try it on MiSoC's SimpleSoC https://github.com/m-labs/misoc/blob/master/targets/simple.py …Thanks. Twitter will use this to make your timeline better. UndoUndo
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