@oe1cxw What fab?
An (actually fabricated) 0.18um chip designed with Yosys (the Verilog synthesis tool I wrote): http://www.reddit.com/r/yosys/comments/2onle4/ …pic.twitter.com/pYQILdu9bw
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@M_Labs_Ltd I don't know. Ask the OP on reddit (see link in my original tweet). I only wrote the tool, did not make the chip..
End of conversation
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@novorado interesting. 2.37x the number of cells but only 1.14x utilization? feel free to contact me per email to discuss this results..
End of conversation
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