#femtorv32 #riscv softcore on IceStick #fpga: running code from Flash and/or BRAM.pic.twitter.com/8hleUmtHRk
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GCC attributes can be used to specify which function goes to BRAM. On the IceStick, we only got 6kB of BRAM, use this wisely !pic.twitter.com/iVTvvfawgZ
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The linker script knows how to interpret it. It puts initialized data and 'fastcode' tagged functions to BRAM.pic.twitter.com/WNaQ3cxuxJ
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Took me a while to understand how the same segment can be put in FLASH (for initialization) and RAM (when running). The AT(_sidata) does the trick, it specifies the "load address", in FLASH memory.
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Verilog sources of
#femtorv32, example programs and explanations are here:https://github.com/BrunoLevy/learn-fpga …1 reply 0 retweets 3 likesShow this thread -
The C runtime (crt0_spiflash.S) copies the initialization data and fastcode segment from FLASH to BRAM.pic.twitter.com/sFZZnI43qd
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Funny: when you play with
#fpga's to design#riscv cores, first you create the hardware, and then you learn how to program it ! Good reference to understand these things:@oe1cxw's picorv/picosoc: https://github.com/cliffordwolf/picorv32/tree/master/picosoc … See start.s/sections.lds (they got *comments*, great !)1 reply 2 retweets 15 likesShow this thread
Claire Xen 🏳️⚧️ 🏳️🌈 🧙🏻♀️ BLM 🏴 🚩 Retweeted Stargirl 🌠
Oh, then you'll *love* this ARM linker script that @theavalkyrie wrote! See 2nd tweet in her thread for the link to her blog post. I wish I had a resource like her post when I had to learn how to do this stuff.https://twitter.com/theavalkyrie/status/1349458442734469123 …
Claire Xen 🏳️⚧️ 🏳️🌈 🧙🏻♀️ BLM 🏴 🚩 added,
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