the one file in yosys that i'm lowkey scared of because it's so hard to understand (and modify even more so) is called "http://simplify.cc " and i think that's beautiful.
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I got through most of a Coursera class on creating EDA tools for place-and-route/etc. The most difficult part (that I sucked at) was simplifying the netlists of gates, even the data structures were hard to think about and work with. So I am not surprised that is the messy file.
This is not a netlist simplifier. This takes an abstract syntax tree for fully-featured Verilog with generate blocks, functions and tasks, loops, and all that stuff and converts it into the AST of a trivial subset of Verilog, that is then converted to a netlist by genrtlil܂cc
