Verilog: TIFF of the futurehttps://twitter.com/oe1cxw/status/1280052819979128833 …
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This isn't really a problem in my day-to-day. Can you provide any practical examples?
There is no System Verilog standard for synthesis. When a synth tool vendor says they "support System Verilog" there is no document where you can look up what that claim even means. Thus different vendors implement different subsets and come up with their own synthesis semantic.
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It's a unified language intended to be used for both Verif and Design, so I think that's intentional. As a designer I've never had a problem with discerning features that are "synthesizable vs. not"- granted, that was in Synopsys/Cadence toolchains, but both co.'s do well here.
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