Verilog: TIFF of the futurehttps://twitter.com/oe1cxw/status/1280052819979128833 …
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System Verilog is fine. I’d even go as far as to call it “good” in a robust EDA toolchain. Verilog 2005 (and earlier) is not. And any toolchain than mandates its use is a problem, IMO.
The System Verilog std doesn't define which part of it is synthesizable. (Unlike Verilog, which has a companion std document that defines the synthesizable subset and synthesis semantic.)
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This isn't really a problem in my day-to-day. Can you provide any practical examples?
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There is no System Verilog standard for synthesis. When a synth tool vendor says they "support System Verilog" there is no document where you can look up what that claim even means. Thus different vendors implement different subsets and come up with their own synthesis semantic.
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