![[ColeJ]](https://pbs.twimg.com/profile_images/1043000626056065024/vDRPnUpt_normal.jpg)
Or G-Code?
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It will be verilog and C :)
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The Devil will always make work for idle hands. The rest of us will be designing circuits in Coq. The circuit is the proof.
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*starts a flamewar on coq vs isabelle*
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System Verilog is fine. I’d even go as far as to call it “good” in a robust EDA toolchain. Verilog 2005 (and earlier) is not. And any toolchain than mandates its use is a problem, IMO.
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The System Verilog std doesn't define which part of it is synthesizable. (Unlike Verilog, which has a companion std document that defines the synthesizable subset and synthesis semantic.)
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Bluespec looked promising but never got traction. The currently active TL-Verilog project is still a WIP. Unless big EDA or big Semi (Apple, BCOM, QCOM etc.) puts their weight on designing a new lang., Verilog/SV will reign supreme. FunFact: thr r still Verilog-XL users :-)
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As long as I don’t need to look at the auto generated Verilog then I can live with that. It would be more bearable if we were talking about VHDL.
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