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As far as the RISC-V spec is concerned all undef instructions are fair game for custom extensions. riscv-formal has an illegal instruction check (rvfi_ill_check) but in its default config it only checks that the zero instruction is illegal (as demanded by the spec).
There is some preliminary work being done on checking ill instruction handling beyond that, and we have already used that to successfully enumerate all custom instructions implemented in an industry core. (even the undocumented ones. ;)
We use our ISS (from our VP) in the fuzzer loop since this allows very fast instr generation. And of course we are already working on an RTL eval / integration.
Cool! Let me know if you are interested in fuzzing RTL on an FPGA (for bigger targets like RocketChip or BOOM). I might be able to spend some time bringing the rfuzz code and dependencies up to date.
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