@oe1cxw If I want a big-ish (10b addr x 16b value) ram/rom in ice40, should I try and trick yosys into figuring out how to map it to BRAMs ... or just make a 1024x4 BRAM macro and try to manually wire my four data nibbles together?
This is hard 
Yosys should have no difficulty mapping this to ice40 brams when using the usual verilog code patterns (same as with all other vlog synthesis tools).
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hm, upgrading to yosys 0.9 seems to be doing much better! re correct patterns: what do I do about a reset line? The example I found had: if (rst) dummy = 0; else ... But ice40 bram docs show no rst line. What's "right" here? No rst wire, handle rst cond elsewhere?
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No rst.
End of conversation
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