If you have used the Xilinx Vivado tools in the last year, did you use C/C++ HLS anywhere in a final design at all (i.e. not counting "just playing around"), or only Verilog/VHDL?
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Thanks everyone for the data point. Context: Xilinx VP of Software Ramine Roane claimes at https://youtu.be/C-_PFbZw_Oo?t=340 … that 2/3 or 3/4 of Xilinx customers are using HLS.https://twitter.com/oe1cxw/status/1226110343824519170 …
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He mixed customers with revenue? Which may very well be a good approximation?
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Yeah, I think it's asking those lines. The majority of people that answered here (including me) are probably not actual customers of xilinx even :)
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It's probably something like: they use HLS in some sort of bootloader or other feature their tools include for some X of models they create. Therefore X% of their customers are "using HLS". Typical barely defendable marketing metric manipulation...
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At the device level power simulation gets its own HLS if not RTL sync'd, you know when driving 24W out and burning 24W on logic to profile as 50W plus deratings...or bail.
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