Here is a quick breakout board for the @latticesemi Crosslink NX QFN72 part that was announced last week.
https://github.com/gregdavill/ArcticKoala …pic.twitter.com/32uXJEvRtf
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Doesn't icepack -s do this?
-s should just slow down the SPI clock to 50 kHz. (Main use case is SW-based logic analyzers.)
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Aah, I was talking about icepack -s which disables the ice40 sending power down after configuring itself, not stopping iceprog from also sending power down after writing flash, which does seem less useful (presumably the ice40 is almost always going to immediately power it up!)
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Ah, I see. That's a different thing. We are talking about the power down command that iceprog sends to the flash it programs. In this case there isn't even an iCE40. The problem is that the FPGA in this system doesn't send a power-up before attempting to read a bit stream.
End of conversation
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