Boards arrived! ^_^pic.twitter.com/6xlEfq5lYu
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I've been using `iceprog` to handle programming of the FLASH. After loading a new bitstream the FPGA doesn't boot until poked by a power cycle. turns out iceprog issues a 'Power Down' command when it completes. And the SPI loader logic on CL-NX does not issue a 'Power Up' :'(
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That's weird. iCE40s do send a power up (and a power down when they are done reading the bitstream). No idea why lattice wouldn't want to do that in all their parts.
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I assume the ice40 SPI master design was all done by Silicon Blue not Lattice? I don't think the ECP5 sends these commands, atleast from my experience with them.
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Good point. Maybe we should make sending the final power down optional? Considering that iceprog is inherently working with a USB-powered device there really is no point in saving a few microamps.
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