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Have you tried adding both a posedge and a negedge event for each async signal, as an ugly workaround? Not that I disagree with you. I think mixing edge and level events would have been clearer and more accurate.
That also simulates incorrectly, because then the falling edge of your async signal is treated like a clock edge.
I've been trying to code this as a single 'always' expression and failed. I wish the following was legal:
// a DFF with async set & clr (set having higher priority) module t ( input clk,set,clr,d, output q ); always @(posedge clk or set or clr) if (set) q <= 1; else if (clr) q <= 0; // Yes, the following line is illegal else if (posedge clk) q <= d; endmodule
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