I disagree. Platform specs require A where it makes sense (such as Linux). There's nothing to gain from forcing tiny embedded cores for inherently non-smp platforms to implement mockup atomics.
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They're necessary to implement synchronization between tasks, which is potentially useful in software on such cores, without a global sw ("kernel") helper. And the amount of logic needed for non-SMP implementation is utterly trivial.
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Replying to @RichFelker @pcwalton
There's nothing you'd need atomics for on an inherently non-smp platform. No matter how trivial the implementation would be, there's no reason to include it on non-smp platforms. Platform specs for platforms that may come in smp variants will certainly require A instructions.
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Yes there is. Atomics are just as important for non-SMP, to implement synchronization between tasks. Otherwise you need complex restart protocol mediated by scheduler.
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Replying to @RichFelker @pcwalton
With non-smp platforms I mean platforms with only one core, not non-symmetric multicore platforms. Sorry, I should have been more clear. Let me rephrase: For platforms on which atomics make any sense whatsoever, the platform spec will require atomics.
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I'm not talking about non-symmetric MP. Pure single core. Atomics are absolutely needed there to implement multitasking without a kernel scheduler doing custom restart sequence mediation.
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See how Linux did atomics on pre-v6 ARM. It was ugly and led to lots of problems later on.
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Replying to @RichFelker @pcwalton
The (under construction) Linux platform specs does require atomics. There are other platforms for which atomics simply do not make sense. For platforms on which atomics make any sense, the platform spec will require atomics.
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An ISA should not be making the determination that nobody will want to do software with context switched tasks that interact through locking/atomic idioms on it. Especially when making the insns work is virtually free on UP.
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Omitting them should be as unthinkable as omitting interrupt masking or undefined instruction exceptions.
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But the ISA isn't doing that. That's the point. It's not the job of the ISA. And a tiny M-mode only RV32E core meant as replacement for AVR or PIC microcontrollers would not need atomics. Thus the platform spec for such cores would not require them.
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I can only repeat: Platform specs for platforms where atomics make sense will require atomics. It doesn't make sense to require them for platforms where there's inherently no need for atomics.
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