Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

FWIW, I think the argument was correct. I wish RISC-V and others would explore ways to do custom extensions that don't clash with ISA encoding space.

It would be nice if we could have a RISC-V do-over that’s just an average, boring ISA, nothing weird or experimental.

I don't see much of it as weird or experimental, just reasonable risc without all the mips badness copied like everyone else did.

What are your thoughts on https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68 … ?

Roughly half is moderately serious, half is pointless pedantry about things that don't matter or complaints about good choices.

Atomics being optional is absolutely wrong. Non-SMP core can implement lr/sc trivially and should be required to. Likewise for mul but not quite as serious since it *can* be emulated in sw.

I disagree. Platform specs require A where it makes sense (such as Linux). There's nothing to gain from forcing tiny embedded cores for inherently non-smp platforms to implement mockup atomics.

They're necessary to implement synchronization between tasks, which is potentially useful in software on such cores, without a global sw ("kernel") helper. And the amount of logic needed for non-SMP implementation is utterly trivial.