I don't see much of it as weird or experimental, just reasonable risc without all the mips badness copied like everyone else did.
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Replying to @RichFelker @oe1cxw
What are your thoughts on https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68 … ?
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Roughly half is moderately serious, half is pointless pedantry about things that don't matter or complaints about good choices.
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Atomics being optional is absolutely wrong. Non-SMP core can implement lr/sc trivially and should be required to. Likewise for mul but not quite as serious since it *can* be emulated in sw.
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The MUL thing is silly because even if the HW ends up doing the same thing as SW in some cases, it’s always at least as efficient, and usually much more. And it’s such a common operation that not having it in base badly fractures binaries—you *have* to use it when available.
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Replying to @stephentyrone @RichFelker and
If you aren’t going to put MUL and barebones atomics in the base ISA, you barely have an ISA; you need to have at least two versions of everything anyway.
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No, you still have the ability for baseline ISA binaries for the weak implementations to run on a proper implementation with mul.
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Yeah, it's possible, but it's catastrophically bad for performance and a big waste of energy.
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Replying to @stephentyrone @RichFelker and
And it's still not any better for the tiny core than just requiring MUL exist to begin with.
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Replying to @stephentyrone @RichFelker and
It's just a dumb decision with no good rationale.
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RISC-V has platform specs for the things you argue should be required in the "base ISA". Please consider that the platforms you have in mind may be vastly different from the platforms other people work on.
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