Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

I don't see much of it as weird or experimental, just reasonable risc without all the mips badness copied like everyone else did.

What are your thoughts on https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68 … ?

Roughly half is moderately serious, half is pointless pedantry about things that don't matter or complaints about good choices.

Atomics being optional is absolutely wrong. Non-SMP core can implement lr/sc trivially and should be required to. Likewise for mul but not quite as serious since it *can* be emulated in sw.

The MUL thing is silly because even if the HW ends up doing the same thing as SW in some cases, it’s always at least as efficient, and usually much more. And it’s such a common operation that not having it in base badly fractures binaries—you *have* to use it when available.

If you aren’t going to put MUL and barebones atomics in the base ISA, you barely have an ISA; you need to have at least two versions of everything anyway.

I mean, FFS, even a Cortex-M0 has MUL for exactly this reason. It can optionally be 32 cycles, but it’s always present.

Can they just issue a revision to make mul non-optional from 2020 onward or whatever?