What I find most funny about ARM moving to allow custom ISA extensions is that in last year's "risc-v basics" smear campaign one of their main arguments against RISC-V was that it'd be unfathomably bad that RISC-V allows custom ISA extensions bc that would lead to fragmentation.
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For instance having them all take a "coprocessor address" operand in a fixed register (after all, there's a huge abundance of registers) that could even be resolved at runtime for the particular cpu model.
That's horrible! If at all, use a CSR. Better, just use instructions >32 bit and give every vendor their unique encoding space. See also my long instruction encoding proposal. https://raw.githubusercontent.com/cliffordwolf/riscv-fanfic/master/riscv-long/riscv-long.md …
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I like the approach I proposed because the address need not be inline in the insn stream but can be loaded from memory at runtime.
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I'd prefer the inlined constants (assuming it's a one shot use thing) because it (ideally) won't pollute the data cache, as opposed to the usual loading from memory, making proper data caching more useful.
End of conversation
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